1. Field of the Invention
The present invention relates generally to electrical circuits, and more particularly but not exclusively to voltage regulators.
2. Description of the Background Art
As its name implies, a voltage regulator regulates voltage delivered to a load. As shown in the example of FIG. 1, a typical voltage regulator draws input current (IIN) from a power source to generate a corresponding output current (Iout). The output current charges an output capacitor (COUT) that provides power to the load (RLOAD). The load is depicted in FIG. 1 as a resistive load for ease of illustration, but may also be non-resistive in other cases. The power source is typically a battery in mobile applications, or the output of an AC to DC converter.
Inrush current is the input current required to charge the output capacitor. At start up, such as when the regulator comes back up from a power OFF state, the output capacitor is discharged. Thus, at start up, the regulator has to generate enough output current to charge the output capacitor (ICHG) and supply current to the load (ILOAD). ICHG is determined by the slew rate (dV/dt) of the output capacitor's voltage. Unless the slew rate is carefully controlled, the inrush current may get overly high—possibly enough to overload the battery or other power source, causing other devices in the system to lose their ability to regulate. Also, because there may be many integrated circuits starting at the same time when the power source is connected or when the system is enabled, it is important for the regulator to minimize current drawn from the power source during start up. A soft start circuit limits inrush current to prevent these problems associated with voltage regulators during start up.
Many different approaches have been developed to limit inrush current. One approach clamps the output of the voltage regulator's error amplifier to a slow ramp to limit the regulator's duty cycle. Another approach slaves the regulator's output to a slow ramp using the same closed loop control as that of a pulse width modulator during normal operation. Both of these approaches suffer from output ringing at the end of the start up sequence and repetitive current limit hits at the beginning of the start up. These approaches in synchronous buck circuits also can discharge the output capacitor if start-up occurs with a partially charged output capacitor, which can occur during momentary power outages. Yet another approach runs the regulator at a fixed current limit until its output reaches the regulated output. This approach results in a large output overshoot at the end of the start up. Worse, if the fixed current limit is lower than the regulator's maximum output current, the regulator may not start up properly (or at all) with some loads. Yet another approach steps or ramps the regulator's current limit in fixed time increments. This approach also has its share of problems, including output overshoot at the end of the start up and variability in start up times.
Accordingly, an improved soft start circuit is needed.